FIG. 1 is a block diagram of a system according to the Background Art having a memory controller with only one port.
Referring to FIG. 1, a system board 100 has a system 110 and an external memory 121. The system 110 includes a memory controller 111, an advanced high-performance bus (AHB) 114, an APB bridge 117, an advanced peripheral bus (APB) 119, a plurality of AHB masters 112 and 115, an AHB slave 116, and an APB slave 118.
Here, the memory controller 111, the AHB 114, the APB bridge 117, the APB 119, and the plurality of AHB master 112, AHB master 115, AHB slave 116, and APB slave 118 support (or use) only one (and the same) protocol, for example, an advanced micro-controller bus architecture (AMBA) protocol.
The memory controller 111 controls data input and output between each of the plurality of AHB master 112, AHB master 115, AHB slave 116, and APB slave 118, and the external memory 121. Also, the memory controller 111 is connected to the AHB 114 through one port 113. Each module AHB master 112, AHB master 115, and AHB slave 116 is connected to the AHB 114. Here, the AHB 114 is used as a system bus.
Accordingly, each of the AHB master 112, AHB master 115, AHB slave 116 and APB slave 118 can write data to or read data from the external memory 121 through a path that includes the system bus 114, the memory controller 111 via port 113, and input/output pins 120. Since in order to write data in and read data from the external memory 121, each AHB master 112, AHB master 115, AHB slave 116, and APB slave 118 should use the system bus 114, the load of the system bus 114 increases and as a result, the entire performance of the system is also lowered.
FIG. 2 is a block diagram of a system according to the Background Art having a multiport memory control. Referring to FIG. 2, the system board 200 has a system 210 and an external memory 224. The system 210 includes a memory controller 211, a system bus (AHB) 213, an APB bridge 216, an APB bus 217, a plurality of AHB master 212, AHB master 214, AHB slave 215, and HPB slave 218, and a plurality of buses 221, . . . , 222.
The memory controller 211 has a plurality of ports 220-1 trough 220-n capable of being connected to each of the plurality of modules. Hereinafter, the memory controller 211 having the plurality of ports 220-1 through 220-n will be referred to as a ‘multiport memory controller’.
All of the multiport memory controller 211, the system bus 213, the APB bridge 216, the APB bus 217, the AHB master 212, AHB master 214, AHB slave 215, and APB slave 218 support (or use) only one (and the same) protocol (for example, the AMBA protocol).